The present invention relates to a semiconductor memory and a method of fabricating the same.
In fabricating reliable semiconductor memories such as DRAMs, it is required to, e.g., decrease the resistance of a capacitor electrode or an interconnection, reduce the fabrication steps to provide inexpensive devices, and planarize the surface in each step, particularly, in a lithography step to widen the process margin for lithography.
One conventional method of fabricating a DRAM having a stacked capacitor is to form an interconnection such as a bit line, form a contact for connecting the storage node electrode of a capacitor and form the storage node electrode, form a capacitor insulating film and a plate electrode, and form an upper interconnection (e.g., IEDM95-907).
When the fabrication method as described above is used, however, although the resistance of the capacitor electrode can be decreased by improving the plate electrode material, planarization when lithography is performed is not realized. Accordingly, it is not easy to fabricate devices, such as 1-Gbit DRAMs, having fine patterns.
Another example of conventional stacked capacitors is described in "P- Y. Lesaicherre et al., "A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO.sub.3 and RIE patterned RuO.sub.2 /TiN storage nodes", IEDM Technical Digest, pp. 831-834, 1994".
The technology described in this reference will be briefly described below with reference to FIGS. 1A to 1D.
First, a 600-nm thick thermal oxide film 162 is formed on a silicon substrate 161, and a contact hole is formed in this thermal oxide film 162. Subsequently, a polysilicon plug 163 is formed in this contact hole (FIG. 1A). A TiN film 164 and a 500-nm thick RuO.sub.2 film 165 are formed on the entire surface by sputtering (FIG. 1B). Next, an island resist mask 166 is formed on the RuO.sub.2 film 165 by using lithography and used as a mask to pattern the RuO.sub.2 film 165 and the TiN film 164 by RIE (FIG. 1C). After a surface treatment is performed for the RuO.sub.2 film 165, an SrTiO.sub.3 film 167 is deposited by ECRMOCVD. Finally, a TiN film and an Al film 168 are formed on the entire surface by sputtering to complete an (Al/TiN/SrTiO.sub.3 /RuO.sub.2 /TiN/poly-Si) stacked capacitor including Al as the plate electrode 168, SrTiO.sub.3 as the capacitor insulating film 167, and the RuO.sub.2 film as the storage electrode 165 (FIG. 1D).
The above description relates only to the fabrication steps of the storage node electrode contact and the capacitor. When the above method is applied to an actual DRAM, the steps of forming a MOSFET and a bit line are added to the above steps, and the polysilicon plug is connected to the source or drain of the MOSFET, rather than the silicon substrate.
In the above conventional technology, however, the storage nodes are separated by patterning the storage node conductive film 165 by using the island resist pattern as a mask. Accordingly, the adjacent storage nodes cannot be made closer to each other than the lithography limit. Consequently, the effective storage node area cannot be well increased.
Also, when a plurality of storage nodes 165 are arranged in a matrix manner as shown in FIG. 2A in the above conventional technology, if the storage node electrodes 165 and storage node contacts 163 are misaligned as shown in a sectional view of FIG. 2B taken along a line 2B--2B in FIG. 2A, a capacitor with a structure in which a plate electrode 168 and the storage node contacts 163 oppose each other via a capacitor insulating film 167 is formed. If this is the case, the combination of the materials of the two components can lead to deterioration of the capacitor characteristics, e.g., deterioration of the insulating properties of the capacitor insulating film 167.
As described above, it is conventionally difficult to perform planarization in lithography and not easy to form fine patterns.
It is also difficult to increase the area of the storage node electrode because the storage nodes cannot be made closer to each other than the lithography limit. Additionally, the capacitor characteristics readily deteriorate due to the misalignment between the storage node electrode and the storage node contact.